1. Field of the Invention
The present disclosure generally relates to the fabrication of semiconductor devices, and, more particularly, to a non-planar exciton transistor (BiSFET) and method for making same.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided and operated on a restricted chip area. In integrated circuits fabricated using metal-oxide-semiconductor (MOS) technology, field effect transistors (FETs) (both NMOS and PMOS transistors, or complementary MOSFET transistors or CMOS) are provided that are typically operated in a switching mode. That is, these transistor devices exhibit a highly conductive state (on-state) and a high impedance state (off-state). FETs may take a variety of forms and configurations. For example, among other configurations, FETs may be either so-called planar FET devices (at 20 nm or earlier CMOS nodes) or three-dimensional (3D) devices, such as finFET devices (at 20 nm or later 14 nm CMOS nodes).
A field effect transistor (FET), irrespective of whether an NMOS transistor or a PMOS transistor is considered, and irrespective of whether it is a planar or 3D finFET device, typically includes doped source/drain regions that are formed in a semiconductor substrate that are separated by a channel region. A gate insulation layer (e.g., dielectric) is positioned above the channel region and a conductive gate electrode is positioned above the gate insulation layer. The gate insulation layer and the gate electrode may sometimes be referred to as the gate structure or gate stack for the device. By applying an appropriate voltage to the gate electrode, the channel region becomes conductive and current is allowed to flow from the source region to the drain region. In a planar FET device, the gate structure is formed above a substantially planar upper surface of the substrate. The gate structures for such planar FET devices may be manufactured using so-called “gate-first” or “replacement gate” (gate-last) manufacturing techniques.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the source region (leading to large leakage current between source and drain in “off state”) and the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded. The short channel effect also increases power dissipation.
To address limitations associated with conventional FETs, various new types of transistor configurations are being explored. One such new transistor configuration is a bilayer pseudo-spin field effect transistor (BiSFET), also referred to as an exciton transistor. An exciton transistor includes first and second planar conducting layers separated by a tunnel dielectric. First and second gate electrodes are capacitively coupled to the conducting layers through gate dielectric layers. The gate electrodes and gate dielectrics are also planar structures. One performance-affecting parameter of an exciton transistor is the dielectric constant of the tunnel dielectric. Also, the planar nature of the exciton transistors is a limiting factor in their scalability.
The present disclosure is directed to various methods and resulting devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.